The present invention is directed to an adder cell having a sum part and a carry part.
Adders are required in a great number of digital logic circuits, for example digital filters, signal processors and microprocessors. The simplest principle for such an adder is the "ripple-carry" method wherein a resulting carry is serially transmitted from one adder cell for the least-significant bit to an adder cell for the most significant bit. The through put time of the carry signal essentially determines the addition time. More involved adder principles such as, for example, the known "carry-look-ahead" method are based on elements of the "ripple-carry" method.
Adder cells for constructing adders for the above-recited addition methods in MOS circuit technology are known, for example, from H. Weiss, K. Horninger, "Integrierte MOS-Schaltungen", Springer-Verlag, Berlin-Heidelberg-New York (1982), pages 188 through 194.
In addition to MOS-circuit technology, a bipolar CMOS (BICMOS) circuit technology has been developed in recent years that is particularly used in time-critical and compact circuits. Advantages both from the MOS as well as from the bipolar circuit technology result from "BICMOS" circuits. High packing densities and no static dissipated power that, for example, are characteristic of circuits of CMOS circuit technology, and a low offset voltage as well as an extremely high processing speed that are characteristic of circuits in ECL or in bipolar circuit technology are favorable features of circuits in "BICMOS" circuit technology. CMOS/bipolar circuits for adders are also disclosed in the technical literature. IEEE Journal of Solid State Circuits, Vol. SC-21, No. 5, October 1986, "CMOS/Bipolar Circuits for 60 MHz Digital Processing" by Takashi Hotta et al discloses a 4-Bit-Arithmetic Unit in FIG. 7 that is composed of half adders, a "carry-generation" circuit and a "carry-propagation" circuit. The "carry-propagation" circuit is disclosed in greater detail in FIG. 8 and on pages 810 and 811, whereby the use of the "BICMOS" circuit technology can also be seen in this figure. The "carry-propagation" circuit contains both MOS transistors as well as a bipolar transistor. CMOS levels between 0 and 5 volts are provided as input signals for this circuit, whereas ECL boosts in the millivolt region can be taken at the output of this circuit.
In the circuit of this latter publication, the conversion of the input level/output level and the logic processing are each undertaken in separate stages. To this end, a bipolar output transistor in FIG. 8 provides for conversion into CMOS level, whereas the remaining MOS transistors of the circuit are responsible for the logic function of the circuit. Such a circuit does not fully exploit the speed advantages of the "BICMOS" circuit technology. The known adder cells in MOS circuit technology are burdened by the disadvantage that either a relatively great plurality of gates are inserted into the carry path that is time-critical for the overall calculating time of an arithmetic unit constructed with such adder cells and/or that the gates inserted into the carry path are component parts of combination gates. In the former instance, the plurality of gates connected in series has an unfavorable influence on the throughput time of carry signals. In the latter instance, the fact that the charging of the capacitance of the carry output does not occur with the required edge steepness due to the relatively high-impedance of the gates which are component parts of combination gates, may have an additionally negative effect under certain conditions.